Timing Optimization of Mixed Static and Domino Logic
نویسندگان
چکیده
A timing optimization algorithm dealing with circuits containing mixed domino and static logic is described. Transistor-level node timing constraints of domino logic is described. The optimization procedure preserves the requirements of maintaining adequate noise margins by constraining the sizing procedure. After sizing, charge-sharing problems are identi ed with a new method and recti ed.
منابع مشابه
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations
| Domino logic is a circuit family that is wellsuited to implementing high-speed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the non-inverting nature of the logic and the complex timing relationships associated with the clock scheme. In this paper, we address several problems along a domino synthesis ow. We mainly consider the problem of partitionin...
متن کاملTiming verification of sequential dynamic circuits
This paper addresses static timing verification for sequential circuits implemented in a mix of static and dynamic logic. We restrict our focus to regular domino logic and footless domino logic, a variant of domino logic. First we derive constraints for proper operation of dynamic gates. An important observation is that for dynamic gates, input signals may start changing near the end of the eva...
متن کاملTiming-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits
The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic cir...
متن کاملOptimal Unate Decomposition Method for Synthesis of Mixed Cmos Vlsi Circuits
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often found in critical paths of various large scale high performance circuits. Yet, due to high switching activity they are not suitable for synthesis of low power circuits. To achi...
متن کاملPath Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efficient timing analysis algorithm. The algorithm uses a single, breadth-first traversal to compute delays in the presence of crosstalk. ...
متن کامل